AMD Zen 4 processors will get IBS support for Linux

There are not a few users who are somewhat dissatisfied with the performance of their AMD Ryzen processor in Linux. This has certainly improved quite a bit in recent years, but Windows still has an advantage, and in some cases a huge advantage, which will soon be scaled back as AMD will add improved support in IBS Zen 4 for the perfection subsystem in Linux.

At the end of last month, AMD sent out a series of patches that were once reviewed, and it was discovered that the company led by Lisa Su plans to implement new IBS extensions for new processors that will fall within the Zen 4 architecture and focus on Linux.

Instruction-Based Sampling or IBS: Why is AMD making improvements like this in Zen 4?

It will be a series of new additions that boil down to two main concepts:

  • data sources.
  • L3 cache is missing filtering.

But why is AMD releasing this now especially for Linux? The problem lies in the implementation of its direct competitor from Microsoft. The Windows kernel introduces many improvements to the Linux kernel, and the restructuring of the L3 cache requires the creation of new bottleneck detection profiles.

Keep in mind that IBS with Zen 4 and with these improvements aims to create more profiles so that developers and associated software have more complete and accurate information about the software.

The goal is to clarify and distinguish instructions that do the job correctly and those that don’t, and isolate issues with them to have a processor pipeline and a cache hierarchy. work optimally. IBS is constantly working with the so-called performance monitoring counters also PMC This records the events that occur with the processor instructions, so timely detection does not degrade performance and thus makes it more consistent.

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Windows uses IBS guidelines better than Linux, so each processor’s PMC, no matter how much it reports, will not provide all the information to the Linux kernel so it can do its job properly, hence this update that AMD itself defines as a path to :

The DataSrc . Extension Provides details of additional data sources for upload/storage operations. Therefore, it adds support for these new bits in the initial performance report/script dump of PMC.

IBS L3 error filtering works by marking the instructions as a “counter overflow” in IBS thus creating a file NMI If tagged instructions cause loss of instruction L3. Samples without an error L3 cache are discarded and the counter is reset to a random value (between 1 and 15 to fetch pmu and between 1 and 127 for reference pmu). This helps reduce sampling costs when the developer is only interested in these samples. One use case for these filtered samples is to feed data to paging in memory systems at different levels.

You can add support for L3 error filtering in the IBS driver via the new pmu themel3“.

This is not only a step forward for AMD in Linux to catch up with Windows in this regard, but it is two steps ahead of Intel, given that Pat Gelsinger includes many “hardware performance counters” in its processors. “So we definitely have to wait Important Cache Changes in Zen 4Especially at the hierarchical level.

via: Voronex

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